1. Field of the Invention
The present invention relates to a high-frequency switching device for carrying out amplification, switching and the like of high-frequency signals in mobile communication apparatuses and the like, and to a semiconductor device obtained by integrating this high-frequency switching device on a semiconductor substrate.
2. Prior Art
In an SPDT (Single-Pole Double-Throw) switching device, one of prior arts of high-frequency switching devices, a resistor element is connected in parallel between the drain and source of each FET constituting a high-frequency switching circuit section as shown in FIG. 15 (for example, refer to Japanese Laid-open Patent Application 2002-232278 (page 13, FIG. 7). In FIG. 15, reference codes 130 to 137 respectively designate depletion-type FETs. Reference codes 250 to 257 respectively designate resistor elements having a resistance value R1. Reference codes 260 to 267 respectively designate resistor elements having a resistance value R2. Reference codes 270 and 271 respectively designate resistor elements having a resistance value R3. Reference codes 510 to 512 respectively designate high-frequency signal input/output terminals. Reference codes 610 and 611 respectively designate control terminals. Reference codes I1 and I2 respectively designate currents.
With this configuration, in the case when a voltage of 3 V is applied to the control terminal 610 and a voltage of 0 V is applied to the control terminal 611, for example, the FETs 130 to 133 are turned ON and the FETs 134 to 137 are turned OFF. Hence, the path from the high-frequency signal input/output terminal 510 to the high-frequency signal input/output terminal 511 can be set in the ON state, and the path from the high-frequency signal input/output terminal 510 to the high-frequency signal input/output terminal 512 can be set in the OFF state.
However, in the configuration of the above-mentioned prior art, with respect to the ON path, a gate forward current flows from the control terminal 610 to the control terminal 611 via the resistor elements 250 to 253, the FETs 130 to 133 and the resistor element 270. The resistor elements 250 to 253, 260 to 263 and 270 are required to be set at a resistance value of 50 kΩ or more so as not to affect the high-frequency characteristics.
When it is assumed that the built-in voltage (forward voltage) of the FET is 0.4 V, the DC potential VB at point B in the figure is represented as follows:
since 3 V−0.4 V=(R1/4+R3)×I1,I1=2.6 V/(R1+4R3)Furthermore, since VB=R3×4I1,VB is represented byVB=10.4×R3/(R1+4R3)  (1)
For example, in the case when the values of the above-mentioned resistor elements 250 to 253, 260 to 263 and 270 are all 50 kΩ, and when it is assumed that the potential at the control terminal 610 is 3 V and that the potential at the control terminal 611 is 0 V, the DC potential at point B is about 2.1 V. Since the ON resistance values of the FETs 130 to 133 are respectively about several Ω and thus negligibly small, the potentials at points B, A and C are nearly equal. As a result, the reverse bias voltage of the FET 134 in the OFF path is about 2.1 V, nearly equal to the voltage at point B. The current 4I1 flowing in the resistor element 270 having the resistance value R3 is 40 μA.
The maximum power Pmax that can be handled by a switch circuit comprising n FETs connected in series is represented byPmax=2{n(VH−VL+VT)}2/Z0  (2)wherein VH designates a high-level voltage applied to the FET, VL designates a Low-level voltage applied to the FET, and VT designates the threshold voltage of the FET. Z0 designates the characteristic impedance of the circuit, generally 50 Ω, and it is assumed that its value is also 50 Ω in this case. When VH=2.1 V and VL=0 V are substituted according to the above-mentioned results, and when the maximum power Pmax is calculated in the case when VT=−0.6 V, the maximum power Pmax is 1.40 W. Hence, the effect of the addition of the resistor elements 260 to 263 and the resistor elements 264 to 267 is hardly obtained.
In order that the DC potential VB at point B is raised and the current consumption is reduced at the same time, a method of increasing the resistance value R3 is thought to be used. However, in the case when the resistance value R3 is increased, there is a problem of resulting in the lowering of the potential VD at point D.
In other words, with respect to the OFF path, a gate reverse current flows from the control terminal 610 via the resistor element 271, the FETs 134 to 137 and the resistor elements 254 to 257. The potential VD at point D in the figure is represented byVD=3.0−(4×R3+6×R2)I2  (3)Since this path is also used as an ON path in some cases, the resistance values of the resistor elements 254 to 257 and 271 are required to be determined so that the conditions are the same as those of the above-mentioned ON path. In order that the potential VB is 2.4 V or more, for example, according to Equation (1), the resistance value R3 is required to be set at 300 kΩ. However, in this case, the potential VD at point D is 1.5 V on the premise that a current of about 1 μA usually flows as the gate reverse current (I2), whereby the maximum power Pmax is lowered further.
As described above, in the prior art, the handling power is apt to be lowered owing to the lowering of the drain-source potential of the FET, and the resistance value R3 cannot be decreased, whereby there is a problem of resulting in the increase of current consumption.
In order to avoid these problems, Japanese Laid-open Patent Application 2002-232278 has proposed a method wherein a capacitor is inserted between the high-frequency signal input/output terminal and the switch circuit section so that they are separated with respect to DC. However, if a capacitor formed in a semiconductor process is directly connected to the high-frequency signal input/output terminal, there are problems of significantly degrading ESD withstand voltage (electrostatic discharge withstand voltage) and increasing the area of a semiconductor chip incorporating the capacitor.